1. Technical Field
The technical field relates to a semiconductor storage device such as a memory card, and in particular, to a semiconductor storage device that guarantees its write speed by carrying out write processing to a plurality of flash memories (non-volatile memories) in parallel.
2. Related Art
Semiconductor storage devices such as SD (Secure Digital) cards, which are card-type recording media having built-in flash memories, are microminiature and microthin. Owing to their handleability, they have conventionally been in widespread use in applications such as digital cameras, mobile devices and the like, for recording data such as images.
As to the SD cards, Speed Classes are defined particularly for use in recording moving images. For example, Class 4 is able to guarantee a write performance of at least 4 MB/s under defined conditions of use.
The defined conditions of use will be described referring to FIG. 2. FIG. 2 shows an explanatory diagram illustrating the alignment of a data recording region in an SD card. As shown in the drawing, in an SD card, user data is defined as a group of AUs (Allocation Units); Wherein one AU is defined as continuous N pieces (where N is a natural number) of RUs (Recording Units). Accordingly, one AU is structured with N pieces of RUs, i.e., RU[0] to RU[N−1].
For example, in a case where RU=64 KB and one AU is structured with sixteen pieces of RUs, the AU is as great as 1 MB. A guarantee value of speed in a case where write processing is carried out to AU, starting from RU[0] to RU[15] in order, is defined as Pw (see SD Specifications Part 1).
Meanwhile, in broadcast and professional fields, images may be recorded with camera recorders having a flash memory. In addition to, an increase in the quality of the recorded image is highly required. In order to meet the requirement, the recording rate must be accelerated. Such fast recording can be realized by providing a plurality of flash memories in a semiconductor storage device, and carrying out write processing to the flash memories in parallel. However, carrying out write processing to a plurality of flash memories in parallel poses a problem of an increase in current consumption in writing.
As a technique that can cope with such a problem, a semiconductor storage device is disclosed in JP-A-6-259320. Specifically, the semiconductor storage device disclosed in JP-A-6-259320 is configured to shift, when carrying out write processing to a plurality of flash memories, the start timing of each write processing such that the write processing to each flash memory does not coincide with the others. Thus, an increase in power consumption is prevented.
Meanwhile, in recent years, the semiconductor storage devices are required to be increased in their capacity to meet an ever increase in size and numbers of write pages. In order to meet the requirement, multilevel flash memories capable of storing equal to or greater than two bits per cell have been commercialized.
FIG. 3 shows an example of the relationship between the number of electrons accumulated in the floating gate of such a multilevel flash memory and the threshold voltage (Vth). As shown in FIG. 3, in a four-level flash memory, the accumulation state of the electrons in the floating gate is managed by four states based on the threshold voltage (Vth). The threshold voltage is the lowest in an erasure state, which is associated with (1, 1). As the electrons accumulate, the threshold voltage discretely increases, the states thereof being associated with (1, 0), (0, 0) and (0, 1) respectively. In this manner, because the threshold voltage increases in proportion to the number of electrons accumulated, by performing control so as to be within a predetermined threshold voltage, it becomes possible to record 2-bit data in one memory cell.
FIG. 4 shows a schematic diagram of one erasure block of a four-level flash memory. The erasure block shown in FIG. 4 is structured with 2×K pages (where K is a natural number). A write process is carried out in ascending order from page number 0. Here, it is assumed that a page having an even page number (2×m is an integer satisfying the relationship 0≦m≦(K−1)) and a page having an odd page number (2×m+1) are in a relationship where they share one memory cell (hereinafter referred to as the cell sharing relationship). In the pages in the cell sharing relationship, the page to be written first is referred to as the 1st record page, and the page to be written next is referred to as the 2nd record page. That is to say, write processing to the page number (2×m) (write processing to the 1st record page) and write processing to the page number (2×m+1) (write processing to the 2nd record page) correspond to charging of electrons to an identical cell. Referring to FIG. 5 showing a state transition diagram of a flash memory cell, in write processing to the 1st record page, control is performed such that the threshold voltage rises only halfway, and in the next write processing to the 2nd record page, control is performed such that the threshold voltage rises to the maximum extent. That is to say, the state of one memory cell of a physical block of a flash memory transits as follows:
(a) the state of the memory cell after data erasure is (1, 1);
(b) the state of the cell after write processing is carried out to the 1st record page is (1, 1) or (1, 0); and
(c) the state of the cell after write processing is carried out to the 2nd record page is (1, 1), (1, 0), (0, 0) or (0, 1).
Hence, write processing to the 2nd record page is carried out by the following four steps:
(c-1) determine whether or not the cell state (the charge state of electrons) immediately before write processing is (1, 0);
(c-2) if the determined cell state (the charge state of electrons) is (1, 0), then Charge electrons to be (1, 0)→(0, 0);
(c-3) determine whether or not the cell state (the charge state of electrons) is (1, 1); and
(c-4) if the determined cell state (the charge state of electrons) is (1, 1), then charge electrons to be (1, 1)→(0, 1).
In the foregoing, (c-1) and (c-3) correspond to read processes, and (c-2) and (c-4) correspond to write processes.
Thus, in write processing to the 2nd record page, the read process and the write process may possibly be carried out for a plurality of times, which makes the write time of the 2nd record page longer than that of the 1st record page. Therefore, simply shifting the write start timing to the 2nd record page in a manner identical to a case of treating the 1st record page results in a time airing which write processing coincides with write processing to another flash memory. As a result, electric power for carrying out write processing to a plurality of flash memories is required. Accordingly, there is a problem that, when a plurality of multilevel flash memories for achieving fast recording are employed, the conventional technique cannot fully reduce the power consumption.